The present invention relates generally to semiconductor device manufacturing and more particularly to methods of manufacturing devices with high-k dielectric materials.
In the semiconductor industry, there is a continuing trend toward high device densities. To achieve these high device densities, small features on semiconductor wafers are required. These features include the width and spacing of source and drain regions, channel regions, and conductive lines.
The features form devices, such as field effect transistors (FETs). An FET includes a source and drain region separated by a channel. A control gate, typically of polysilicon, is formed over the channel and is electrically separated from the channel by a gate dielectric layer, which is typically silicon dioxide. A current will either flow or not flow across the channel between the source and the drain depending on the voltage applied to the control gate.
A limitation on the degree to which FETs can be scaled down is the difficulty of forming very thin gate oxides. As FETs become progressively smaller, the electrical capacitance of the gate dielectric must be proportionally increased. Using conventional gate oxide material, which is silicon dioxide, a layer of about 1 nm or less is required for devices with 0.10 xcexcm features. At such small thicknesses, non-uniformity of the gate oxide layer, tunneling of electrons through the gate oxide layer, and diffusion of dopants through the gate oxide layer become problematic.
In view of these issues, it has been proposed to replace silicon dioxide gate dielectrics with so called high-k dielectrics. High-k dielectrics have higher permittivity than silicon dioxide, whereby a gate layer providing a given degree of capacitance can be made thicker than an equivalent layer of silicon dioxide. High-k dielectrics typically have a permitivity of at least about 3 times that of silicon dioxide, whereby the gate dielectric is at least about three times thicker.
An obstacle to the use of high-k dielectrics has arisen at the point of pattern transfer to a layer of the high-k dielectric. Conventional etching processes that might be effective to remove the high-k dielectric, processes such as reactive ion etching and wet etching with hydrofluoric acid have proven ineffective at removing the high-k while avoiding damaging either the underlying insulating structures, such as field oxide islands that become exposed as the high-k layer is patterned, or overlying conductive layers, such as a layer of polysilicon which forms a transistor gate. There is an unsatisfied need for methods of etching high-k dielectrics without unduly damaging exposed polysilicon or underlying field oxides.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention provides systems and methodologies for calibrating transistor circuits and devices, by which the above and other shortcomings associated with the prior art are mitigated or overcome.
One aspect of the invention relates to a method of etching a high-k dielectric. The method involves removing an exposed portion of a high-k dielectric layer from a substrate by wet etching with a solution comprising water, a strong acid, an oxidizing agent, and a fluorine compound. The etching solution provides selectivity towards the high-k film against insulating materials and polysilicon and is therefore useful in manufacturing FETs.
In accordance with one aspect of the present invention, a multi-step etch process is employed, wherein one type of etchant is used to remove a bulk portion of an exposed region of the high-k dielectric film in a time efficient manner. For example, a substantial portion of the high-k film, about 70-90% thereof is removed using a diluted HF mixture such as about 0.5% HF in a solution such as de-ionized water.
Upon completing the bulk removal, a different etch chemistry is employed which exhibits an advantageously high selectivity towards other materials present during the etch, for example, polysilicon and silicon dioxide. The second etch comprises an aqueous solution that comprises a strong acid, an oxidizing agent and a fluorine compound. The ratio of these chemicals provides a substantially expedient removal of the remaining portion of the high-k dielectric film without an appreciable loss of silicon dioxide or polysilicon. Due to the advantageously high selectivity of the second etch, an overetch of the high-k dielectric film may be employed to ensure complete removal thereof, thereby avoiding knock-on implantation of metal during subsequent implantation steps, inhibition of silicide formation, an increase in the gate-to-drain capacitance (Cgd), and the appearance of fringing fields at the corner of the gate.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.